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PRODUCT DATASHEET
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1.32 Gbit/s Serial Link Transmitter and Receiver
The GigaSTaR (Gigabit/s Serial Transmitter and Receiver) is a universal high-speed point-to-point communication link. It consists of two devices, the Transmitter INGT165B and the Receiver INGR165B. The INGT165B Transmitter converts parallel data up to 36-bit to a serial bit-stream. The differential CML (Current Mode Logic) outputs can directly drive Shielded-Twisted-Pair (STP) cables for distances up to 50 meters and can directly interface to inputs of fiber optic modules to span longer distances. The INGR165B Receiver converts the serial bit-stream to the original parallel data format, fully transparent and without protocol overhead. Link-synchronization, bit-stream coding/decoding, clock-/framerecovery and parity-check are managed by internal high-speed resources. GigaSTaR(R) links can be operated in parallel, scaling the bandwidth in multiples of 1.188 Gbit/s (payload data rate).
(R)
INGT165B INGR165B
INGT165B
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INGR165B
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12x12 mm, 196 PBGA packages
FEATURES
36-bit 33 MHz parallel data interface (3.3V CMOS) Variable payload data transfer rate up to 1.188 Gbit/s Internal RF clock-generation and clock-recovery (PLL) Integrated DC-balanced coding for AC coupling Integrated cable equalizer (INGR165B) Built in parity check Low latency of 40 ns per device (type) Differential, low-swing CML-signals for the serial link High signal robustness, EMI and noise immunity Direct interfacing to 50/100 Ohm cables and fiber optic modules Single +3.3V DC supply Low power dissipation of 1 W per device (type) Ambient operating temperature - 40C to +85 C

APPLICATIONS
High-speed scanning / printing (photo, exposure- and security systems) Mass storage connections High-speed and multi-channel imaging Telecommunication switches High-speed sensors / actuators Industrial Control High-resolution panel links Data broadcast (Video Server)

RDCLK
WRCLK GigaST#R Transmitter INGT165B
PDATA[35..0]
GigaST#R Receiver INGR165B
PDATA[35..0]
Figure 1: GigaSTaR(R) Link
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1. GigaSTaR(R) LINK DESCRIPTION
The GigaSTaR(R) link is designed for reliable, high-speed, low-latency data transmission. All functions for data transfer management including the high-frequency blocks are fully integrated in the Transmitter and Receiver devices. Both devices feature a 36-bit "user-friendly" parallel interface with standard logic levels (3.3V CMOS) for easy adaptation to any application. The link supports an effective (sustained) data rate up to 148.5 MByte/s at the parallel interface, which translates to a serial bit stream of max. 1.188 Gbit/s (payload data rate). With 4 additional bits for linksynchronization, DC-balancing and parity check the maximum bit rate at the serial I/Os is 1.32Gbit/s, for an overall link efficiency of 90 percent. With only 40 ns propagation delay time each for the Transmitter and Receiver, the typical overall latency for a GigaSTaR(R) link with STP copper cable is: latency [ns] = 2 * 40 ns + 4ns/m * cable-length [m] For example, the latency is about 160 ns for a 20 meter connection with Shielded-Twisted-Pair (STP) copper cable.
1.1 CLOCK SYSTEM
The serial bit clock frequency of 1320 MHz is generated by internal PLLs. The Transmitter and Receiver each require an external 66 MHz reference clock. A continuous phase alignment in the Receiver ensures that the receive clock is synchronous to the transmit clock.
1.2 PARALLEL DATA FORMAT
Both the GigaSTaR(R) Transmitter and Receiver feature a synchronous 36 bit parallel interface. The maximum frequency at this interface is 33 MHz, equivalent to a period of 30.3 ns for the WRCLK/ RDCLK signals. Additional parity I/Os allow the transfer of an optional external parity bit synchronous with the parallel data. If an external parity bit is provided, the Transmitter validates the signal before the start of the transmission. If no external parity bit is available, the Transmitter generates this signal automatically. Parity error flags are provided at both the Transmitter and Receiver devices.
1.3 SERIAL DATA FORMAT
The serial data stream is DC-balanced to support capacitive (AC) coupling for full DC isolation of the link. This is performed by proprietary coding in the Transmitter device.
1.4 LINK MEDIA (COPPER OR FIBER)
The GigaSTaR(R) Transmitter and Receiver are each equipped with a robust high-speed interface which can be directly connected to impedance-controlled cables (STP or coax), transmission lines or fiber optic modules. Initial evaluations with 50 Ohm (100 Ohm differential) Shielded-Twisted-Pair (STP) cables already have proven reliable transmissions at distances of up to 50 meters and beyond (Reference-product: GGSC1608-05/-10/-15/-20/-30/-40/-50, W.L. Gore & Associates). Copper media require a serial line termination (R/L combination) at the inputs of the GigaSTaR(R) Receiver for optimized performance, please refer to the ING_TRC piggyback board data sheet for reference values. The capacitors for AC coupling of the serial lines have to be 100nF and are to be applied at both ends of the link medium (see also figure 1). It is required to use ceramic RF capacitors. With conventional 850 nm fiber optic modules (AC in/out, 3.3V PECL) and multimode fiber distances up to 550 meters have been achieved, see also datasheet of the ING_TRF fiberoptical piggyback board.
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2. GigaSTaR(R) INGT165B TRANSMITTER
2.1 BLOCK DIAGRAM
OSC LOCK EXTRC1 EXTRC2
1.32 GHz CLOCK GENERATOR
RDCLK PDATA[35..0] PARITY VALID
CLOCK
Tx_SHIFTER FRAMER
SERIALIZER
SDATA SDATA#
SHIFTER CTRL
HEADER
MUX CTRL
(FLOW CONTROL & HEADER GENERATOR )
RESET#
PERR#
PARGEN
FLAGI
SYNGEN
Figure 2: GigaSTaR(R) Transmitter Block Diagram
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2.2 INGT165B TRANSMITTER PARALLEL INTERFACE
The Transmitter parallel interface is designed to support different operating modes providing a maximum flexibility for the design of the application interface.
RESET# LOCK SYNGEN
PARGEN FLAGI VALID RDCLK PDATA[35..0] PARITY PERR#
GigaST#R INGT165B TRANSMITTER
SDATA
SDATA#
Figure 3: GigaSTaR(R) Transmitter Parallel Interface
2.2.1 Control Signals
RESET# is an asynchronous active low reset signal. After a power-up sequence and activation of the reference clock, RESET# has to be kept low for at least 1 ms. The link is operational as soon as the LSYNC# signal of the Receiver is going low. LOCK = '1' indicates that the internal PLL is locked. If LOCK is de-asserted the Transmitter is not ready. PARGEN = '1' activates the internal parity generation. In this mode the PARITY input pin is ignored. An internal parity bit is generated and transmitted. The positive edge of FLAGI sets an internal flag which is inserted at the end of the data word currently in transmission. The Receiver decodes the flag out of the serial bit-stream and toggles the level of the FLAGO output. This signal can be used to mark the end of a data frame. VALID = '1' indicates to the Transmitter that data are available. With the assertion of VALID the RDCLK starts to run. PDATA[35..0] is registered at each rising edge of RDCLK. De-asserting VALID disables RDCLK and stuffing patterns are transmitted over the GigaSTaR(R) link to maintain synchronization. PERR#: description see 2.2.2 Note: the SYNGEN input is reserved for optional functions and has to be set to "0".
2.2.2 Data Interface
The GigaSTaR(R) parallel data interface is designed to support a variety of application interfaces. It provides read clock (RDCLK) pulses with a cycle time of 30,3 ns (corresponding to 33MHz) to the application output buffers like FIFOs, memory devices, ASICs or PLDs. A data word at the parallel interface consists of 36 data bits. If PARGEN = '0' the transmitting application has to supply the data's parity at the input PARITY synchronous to the parallel data. PARGEN = '1' logic high activates internal parity generation and the PARITY input pin is ignored. If the application supplies its own parity bit (PARGEN is de-asserted), PERR# reports any mismatch between the internally generated and the external PARITY signal. If this is the case, the internally generated (correct) PARITY is transmitted with the data word. PERR# is always inactive when PARGEN = '1'. The default value of PERR# after reset is `1'.
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2.2.3 Data Burst Transfers
The data burst timing provides the full data rate of 148.5 MByte/s. VALID is asserted when the first data is valid at PDATA[35.0]. With every rising edge of RDCLK the PDATA inputs are registered, serialized and transmitted. VALID can remain asserted as long as new data are available. In the timing diagram PARGEN is de-asserted and the application delivers the PARITY bit synchronously to the data word.
LOCK#
RESET#
t2-2
t2-1
t5
t5
VALID RDCLK PDATA [35..0] PARITY DW1 PARITY1 DW2 PARITY2 DW3 PARITY3
t2 t1 t3
t4
Figure 4: INGT165B Data Burst Timing Diagram
Parameter t1 t2 t2-1 t2-2 t3 t4 t5 Description Setup time PDATA and PARITY to RDCLK rising edge VALID active to first rising RDCLK edge VALID high state LOCK# / RESET# high state before Tx operational * PDATA and PARITY hold time RDCLK cycle time (without assertion of FLAGI) Rising RDCLK edge to sampling window for VALID state (VALID=0: exit BURST mode, VALID=1: continue BURST mode) Min. 9 9 5 50 9 18 Typ. 6 12 4 6 30.3 20 Max. 14 Unit ns ns ns s ns ns ns
22
Note : For timings with assertion of FLAGI, please see section 3.2.5 *A dislock pulse generates an internal transmitter reset. Therefore both signals have to be at least 50us at high state before transmitter is operational. Table 1: INGT165B Data Burst Timing Parameters (under recommended operating conditions)
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2.2.4 Single Word Transfers
Single Word Transfers are used to support lower data rates than the maximum parallel data rate of 148.5 MByte/s. VALID has to be de-asserted after the parallel read cycle signaled by one RDCLK pulse. Only one data word is transmitted. In the timing diagram PARGEN is de-asserted and the application delivers the PARITY bit synchronously to the data word.
LOCK#
RESET#
t7-2
t7 t7-1
t10
VALID RDCLK PDATA [0..35] PARITY
t9
DW1 PARITY1
t6
t8
Figure 5: INGT165B Single Word Transfer Timing Diagram
Parameter t6 t7 t7-1 t7-2 t8 t9 t10
Description Setup time PDATA and PARITY to RDCLK rising edge VALID active to rising RDCLK edge VALID high state LOCK# / RESET# high state before TX operational * PDATA and PARITY hold time RDCLK high state (without assertion of FLAGI) Rising RDCLK edge to sampling window for VALID state (VALID=0: continue single word mode, VALID=1: enter BURST mode)
Min. 9 9 5 50 9 14 18
Typ. 6 12 4 6 15 20
Max. 14
16 22
Unit ns ns ns s ns ns ns
Note : For timings with assertion of FLAGI, please see section 3.2.5 * A dislock pulse generates an internal transmitter reset. Therefore both signals have to be at least 50us at high state before transmitter is operational. Table 2: INGT165B Single Word Transfer Timing Parameters (Under recommended operating conditions)
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3. GigaSTaR(R) INGR165B RECEIVER
3.1 BLOCK DIAGRAM
OSC LOCK EXTRC1 EXTRC2
1.32 GHz CLOCK GENERATOR
CLOCK
WRCLK RX_SHIFTER PDATA[35..0] PARITY
SDATA SDATA#
DE_SERIALIZER DEFRAMER
RES
FLAGO
LSYNC#
PERR#
RESET#
Figure 6: GigaSTaR(R) Receiver Block Diagram
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3.2 INGR165B RECEIVER PARALLEL INTERFACE
RESET# LOCK EQLSEL SDATA
GigaST#R INGR165B RECEIVER
LSYNC# FLAGO WRCLK
SDATA#
PDATA[35..0] PARITY PERR#
Figure 7: GigaSTaR(R) Receiver Parallel Interface
3.2.1 Control Signals
RESET# is an asynchronous active low reset signal. After a power-up sequence and activation of the reference clock, RESET# has to be kept low for at least 1 ms. The link is operational as soon as the LSYNC# signal is going low. LOCK = '1' indicates that the internal PLL is locked. If LOCK is de-asserted, the Receiver is not ready. EQLSEL activates the internal equalizer to support extended cable lengths above 10 meters. FLAGO is the sideband signalling output flag, for timing details see 3.2.5. The default state of FLAGO after reset is `0'. The status bit LSYNC# is asserted if the GigaSTaR(R) Receiver is synchronized to the incoming bit-stream. If the Receiver is not synchronized correctly, LSYNC# is de-asserted. The receiver permanently computes the parity over each transmitted word and compares it with the transmitted parity bit. A mismatch of both parity information indicates a transmission failure and the signal PERR# is asserted for one data cycle. LSYNC# is de-asserted and the Receiver starts to re-synchronize the link.
3.2.2 Data Interface
The parallel interface is designed to support a variety of application interfaces. It provides a sequence of write clock (WRCLK) pulses with a cycle time of 30.3 ns (corresponding to 33MHz) which is used to clock data into the remote application's input buffer like a FIFO, memory devices or directly into an ASIC or PLD. A data word at the parallel interface consists of 36 data bits. The data's parity is always available synchronous to the data at the PARITY output. The application may use the parity bit for additional information about the data's validity. As long as data with a wrong parity are transmitted, the Receiver is not synchronized with the Transmitter, and the LSYNC# signal is de-asserted.
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3.2.3 Data Burst Transfers
The data burst timing is used to support the full data rate of 148.5 MByte/s. PDATA[35..0] and PARITY are updated with each rising edge of WRCLK.
RESET# LOCK LSYNC# WRCLK PDATA[35..0] PARITY PERR# DW1 PARITY1
t 11 t12
DW2 PARITY2 DW3 PARITY3
Figure 8: INGR165B Data Burst Timing Diagram
Parameter t11 t12 Description Rising edge WRCLK to PDATA and PARITY bit valid WRCLK cycle time (without assertion of FLAGI) Min. Typ. 1 30.3 Max. 4 Unit ns ns
Note: For timings with assertion of FLAGI, please see section 3.2.5 Table 3: INGR165B Data Burst Timing Parameters (Under recommended operating conditions)
3.2.4 Single Word Transfers
Single Word Transfers are used to support lower data rates. Every time a new data word is received the WRCLK signal generates one clock pulse.
R E SE T # L O CK L S Y N C# WR C LK P D AT A[3 5..0] P A RIT Y P E RR #
t14
D W1 P A RIT Y 1
t13
Figure 9: INGR165B Single Word Transfer Timing Diagram
Parameter t13 t14
Description Rising edge WRCLK to PDATA and PARITY valid WRCLK high state
Min. 14
Typ. 1 15
Max. 4 16
Unit ns ns
Table 4: INGR165B Single Word Transfer Timing Parameters (under recommended operating conditions)
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3.2.5 FLAGI / FLAGO Timing
With the FLAGI / FLAGO signals a mechanism is provided to implement a sideband signalling. Each rising edge at the Transmitter's input FLAGI toggles the FLAGO output of the Receiver. The timing diagram for the FLAGI/FLAGO signal is shown in combination with the Transmitter signals. Note that when the FLAGI signal is asserted, the following RDCLK high state time span is enlarged by app. 6 ns. At the Receiver, the WRCLK low state time span is enlarged by app. 6 ns when the FLAGO output toggles. In the diagrams below, the PARGEN is active at the Transmitter, therefore no external parity is provided.
TRANSMITTER
RESET# PARGEN FLAGI VALID RDCLK PDATA [35..0]
t 15
t16
t17
DW1*
DW2
DW3*
DW4
DW5
t18
RECEIVER
RESET# LOCK LSYNC# WRCLK PDATA [35..0] PARITY FLAGO DW1* PARITY1 DW2 PARITY2
t18
DW3* PARITY3
DW4 PARITY4
DW5... PARITY5...
t19 t20 t20
Note : * indicates the data words [DW1, DW3] that are marked by the FLAGI signal. Figure 10: INGT165B / INGR165B FLAGI and FLAGO Timing Diagram
Parameter t15 t16 t17 t18 t19 t20 Description Rising edge of RDCLK to rising edge of FLAGI FLAGI minimum high state FLAGI minimum low state RDCLK cycle time after assertion of FLAGI (one cycle only) Rising edge of WRCLK to PDATA, PARITY and FLAGO valid WRCLK cycle time for data word marked by FLAGO toggle Min. 0 Typ. 4 4 36 1 36 Max. 18 6 6 4 Unit ns ns ns ns ns ns
Table 5: INGT165B / INGR165B FLAGI and FLAGO Timing Parameters
(under recommended operating conditions)
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3.2.6 Parity Error (Reporting) Timing
t21
LSYNC # WRCLK PDATA [35..0] PERR# DW1 DW2
Corrupt Data
Figure 11: INGR165B Parity Error (reporting) timing
t22
Parameter t21 t22
Description Rising edge of WRCLK marking the corrupt data word to rising edge of LSYNC# Rising edge of WRCLK marking the corrupt data word to falling edge of PERR#
Min.
Typ. 30 3
Max. 40 6
Unit ns ns
Table 6: INGR165B Parity Error (reporting) timing (under recommended operating conditions)
3.2.7 Header/Frame Error (Reporting) Timing
t23
LSYNC # WRCLK PDATA [35..0] PERR# DW1 DW2
Data with corrupt header
t24 t25
Figure 12: INGR165B Header/Frame Error (reporting) timing
Parameter t23 t24 t25
Description Rising edge of WRCLK marking the corrupt data header to rising edge of LSYNC# Rising edge of WRCLK marking the corrupt data header to falling edge of PERR# PERR # low state
Min. 0
Typ. 11 1,5 3
Max. 15
Unit ns ns ns
Table 7: INGR165B Header/Frame Error (reporting) timing (under recommended operating conditions)
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4. DEVICE SPECIFICATION
4.1 ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings define values beyond which damage to the device may occur. Inova Semiconductors may not be held liable for any product degradation or damage caused by a violation of the absolute maximum ratings. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above those indicated in the recommended operating conditions is not guaranteed.
Parameter DC Supply Voltage Input Voltage I/O Current (DC or transient any pin) Symbol VCC VIN ID Min. -0.5 -0.5 -20 -45 -55 Max. +4.2 VCC+0.5 +20 +140 +150 220 / 10 2000 800 Units V V mA Note See handling precautions (6) See handling precautions (6)
Junction Temperature (under bias) Tj Storage Temperature Tstg Soldering Temp./Time TSLD / tSLD Static Discharge Voltage (CMOS dig. I/O VSDCMOS versus respective GND & Supply rails) Static Discharge Voltage (all other pin VSDCML combinations including CML I/O pins )
C C C / sec V Human Body Model V Human Body Model
Table 8: Absolute Maximum Ratings
4.2 RECOMMENDED OPERATING CONDITIONS
Parameter DC Supply Voltage Input Voltage CML Output Current CMOS Output Current Junction Temperature (under bias) Ambient Temperature Symbol VCC VIN IOUTCML IOUTCMOS Tj Ta Min. +3.15 0 -10 -10 -40 -40 Max. +3.45 Vcc +10 +10 +125 +85 Units V V mA mA C C Note VCC =3.3V 0.15V
Table 9: Recommended Operating Conditions
4.3 ELECTRICAL SPECIFICATION
4.3.1 AC - Characteristics (under recommended operating conditions, Reference Clock Frequency = 66 MHz)
Parameter Input capacitance, any pin (@ 66 MHz) Serial Transmission Data Rate Serial Payload Data Rate Parallel Interface Data Rate Serial Bit Width CMOS Output Rise / Fall Time (CL = 10 pF) Min. Typ. 1.5 1.32 1.188 148.5 757.6 5 Max. 3 Units pF Gbit/s Gbit/s MByte/s ps ns
10
Table 10: AC - Characteristics
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4.3.2 DC - Characteristics (under recommended operating conditions)
Parameter CMOS Input High Voltage CMOS Input Low Voltage CMOS Input High Current CMOS Input Low Current EQLSEL/OSC Pin High Current EQLSEL/OSC Pin Low Current CMOS Output High Voltage CMOS Output Low Voltage CMOS Output High Current CMOS Output Low Current LOCK Output High Current LOCK Output Low Current INGT165B Supply Current INGR165B Supply Current INGT165B Power Dissipation INGR165B Power Dissipation Symbol VIH VIL IIH IIL IIH IIL VOH VOL IOH IOL ILH ILL ICCTX ICCRX PDTX PDRX Test Condition VIN = Vcc VIN = 0 V VIN = Vcc VIN = 0 V IOH = -0.5 mA IOL = 1.5 mA VOH = 0.9Vcc VOL = 0.1Vcc VOH = 0.9Vcc VOL = 0.1Vcc CMOS output load = 10 pF CMOS output load = 10 pF Max. data transmission rate Max. data transmission rate Min. 2.6 -1 -1 -10 -10 0,95Vcc -3 3.5 -1 1.5 -5 6 -2.5 3 340 300 1.1 1 Typ. Max. 0.7 1 1 40 10 0,05 Vcc Unit V V A A A A V V mA mA mA mA mA mA W W
430 360 1.5 1.25
Table 11: DC - Characteristics (under recommended operating conditions)
Note : A floating CMOS input can result in heavy internal current draws. To achieve best performance for unused inputs an external pull-up should be added.
4.3.3 Reference Clock Specification (Ta = -40 to 85 C; Vcc = 3.15 to 3.45 V)
Parameter Nominal Frequency Frequency Tolerance Duty Cycle Symbol fOSC FTOL Min. -100 40 Typ. 66 Max. +100 60 Unit MHz ppm % Note
Table 12: Reference Clock Specification
4.3.4 External Loop Filter Specification (Ta = -40 to 85 C)
RLF1 EXTRC1
CLF
RLF2 EXTRC2
The internal PLLs of the INGT165B and the INGR165B devices require an external RC loop filter. It is not required to use dedicated RF R- and C-components, std components will perform correctly.
Parameter Loop Filter Capacity Loop Filter Resistor 1 Loop Filter Resistor 2 Symbol CLF RLF1 RLF2 Value Tx 1F 0 Ohm 0 Ohm Value Rx 1F 47 Ohm 47 Ohm Note Chip Capacitor (Ceramic )
Table 13: External Loop Filter Specification
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4.3.5 Transmitter and Receiver Timing Parameters (under recommended operating conditions)
Parameter t1 t2 t2-1 t2-2 t3 t4 t5 t6 t7 t7-1 t7-2 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 Description Setup time PDATA and PARITY to RDCLK rising edge VALID active to first rising RDCLK edge VALID high state LOCK# / RESET# high state before Tx operational PDATA and PARITY hold time RDCLK cycle time (without assertion of FLAGI) Rising RDCLK edge to sampling window for VALID state (VALID=0: exit BURST mode, VALID=1: continue BURST mode) Setup time PDATA and PARITY to RDCLK rising edge VALID active to rising RDCLK edge VALID high state LOCK# / RESET# high state before TX operational PDATA and PARITY hold time RDCLK high state (without assertion of FLAGI) Rising RDCLK edge to sampling window for VALID state (VALID=0: continue single word mode, VALID=1: enter BURST mode) Rising edge WRCLK to PDATA and PARITY bit valid WRCLK cycle time (without assertion of FLAGI) Rising edge WRCLK to PDATA and PARITY valid WRCLK high state Rising edge of RDCLK to rising edge of FLAGI FLAGI minimum high state FLAGI minimum low state RDCLK cycle time after assertion of FLAGI (one cycle only) Rising edge of WRCLK to PDATA, PARITY and FLAGI valid WRCLK cycle time for data word marked by FLAGO toggle Rising edge of WRCLK after the corrupt data word to rising edge of LSYNC# Rising edge of WRCLK marking the corrupt data word to falling edge of PERR# Rising edge of WRCLK marking the corrupt data header to rising edge of LSYNC# Rising edge of WRCLK marking the corrupt data header to falling edge of PERR# PERR # low state Min. 9 9 5 50 9 18 9 9 5 50 9 14 18 Typ. 6 12 4 6 30.3 20 6 12 4 6 15 20 1 30.3 1 15 4 4 36 1 36 1 3 0 1,5 3 Max. 14 Unit ns ns ns s ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
22
14
16 22 4 4 16 18 6 6 4 5 6 13
14 0
Table 14: Transmitter and Receiver Timing Parameters (under recommended operating conditions)
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INGT165B TRANSMITTER PIN DEFINITION
Pin Name PDATA[0] PDATA[1] PDATA[2] PDATA[3] PDATA[4] PDATA[5] PDATA[6] PDATA[7] PDATA[8] PDATA[9] PDATA[10] PDATA[11] PDATA[12] PDATA[13] PDATA[14] PDATA[15] PDATA[16] PDATA[17] PDATA[18] PDATA[19] PDATA[20] PDATA[21] PDATA[22] PDATA[23] PDATA[24] PDATA[25] PDATA[26] PDATA[27] PDATA[28] PDATA[29] PDATA[30] PDATA[31] PDATA[32] PDATA[33] PDATA[34] PDATA[35] PARITY RDCLK VALID RESET# FLAGI PARGEN SYNGEN PERR# LOCK OSC SDATA SDATA# EXTRC1 EXTRC2 GND--D GND--ID GND--IA GND--A0 GND--A1 VCC--D VCC--ID VCC--IA VCC--A0 VCC--A1 Pin # A5 B5 A4 B4 A3 B3 A2 B2 B1 C1 D2 E3 D1 E2 E1 F2 G3 G1 H3 H2 J1 J2 L1 K3 K2 M1 L3 M2 N2 P2 N3 P3 N4 P4 N5 P5 C6 B6 N6 A6 M6 N1 D3 P6 C7 A10 K12 J14 H13 H12 C2, C5, F3, G2, J3, L2, M5 A7, P7 G6, G7, G8, G9, J6, J7, J8, J9, K7, K8 C9, C11, D10, D14, K14, L10 G12, G13 C4, F1, H1, K1, M4 B7, N7 E7, E8, E9, E10, F6, F7, F8, F9, F10, F11, H6, H7, H8, H9 A11, D9, L9, L11, M9 H14, J11 Direction INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS INCMOS OUTCMOS INCMOS INCMOS INCMOS INCMOS INCMOS OUTCMOS OUTCMOS INCMOS OUTCML OUTCML GND GND GND GND GND VCC VCC VCC VCC VCC Active High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High Low High High High Low High Description Parallel data input, Bit 0 Parallel data input, Bit 1 Parallel data input, Bit 2 Parallel data input, Bit 3 Parallel data input, Bit 4 Parallel data input, Bit 5 Parallel data input, Bit 6 Parallel data input, Bit 7 Parallel data input, Bit 8 Parallel data input, Bit 9 Parallel data input, Bit 10 Parallel data input, Bit 11 Parallel data input, Bit 12 Parallel data input, Bit 13 Parallel data input, Bit 14 Parallel data input, Bit 15 Parallel data input, Bit 16 Parallel data input, Bit 17 Parallel data input, Bit 18 Parallel data input, Bit 19 Parallel data input, Bit 20 Parallel data input, Bit 21 Parallel data input, Bit 22 Parallel data input, Bit 23 Parallel data input, Bit 24 Parallel data input, Bit 25 Parallel data input, Bit 26 Parallel data input, Bit 27 Parallel data input, Bit 28 Parallel data input, Bit 29 Parallel data input, Bit 30 Parallel data input, Bit 31 Parallel data input, Bit 32 Parallel data input, Bit 33 Parallel data input, Bit 34 Parallel data input, Bit 35 Parity input Read clock. PDATA[35..0] is registered at rising edge Data valid signal Asynchronous reset signal Set FLAG Generate parity internally Reserved for future functionality, has to be set to `0' Parity error PLL lock indication Reference clock input, 66MHz Differential serial high-speed CML output Differential serial high-speed CML output External loop filter pin1 External loop filter pin2 Digital chip (CMOS) power supply GND Chip interface digital chip power supply GND Chip interface analog chip power supply GND Analog chip (Bipolar) power supply GND Analog chip (Bipolar) PLL circuit power supply ground Digital chip (CMOS) power supply VCC Chip interface digital chip power supply VCC Chip interface analog chip power supply VCC Analog chip (Bipolar) power supply VCC Analog chip (Bipolar) PLL circuit power supply VCC
Table 15: GigaSTaR(R) INGT165B Pin Definition
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INGT165B / INGR165B
INGT165B TRANSMITTER PIN ASSIGNMENT (TOP VIEW)
1 A B C D E F G H J K L M N P
N. C.
2
PDATA [6]
3
PDATA [4]
4
PDATA [2]
5
PDATA [0]
6
RESET#
7
GND_ID
8
N. C.
9
N. C.
10
OSC
11
VCC_A0
12
N. C.
13
N. C.
14
N. C.
PDATA [8] PDATA [9] PDATA [12]
PDATA [7] GND_D
PDATA [5] N. C.
PDATA [3] VCC_D
PDATA [1] GND_D
RDCLK
VCC_ID
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
PARITY
LOCK
N. C.
GND_A0
N. C.
GND_A0
N. C.
N. C.
N. C.
PDATA [10]
SYNGEN
N. C.
N. C.
N. C.
N. C.
N. C.
VCC_A0
GND_A0
N. C.
N. C.
N. C.
GND_A0
PDATA [14] VCC_D
PDATA [13] PDATA [15]
PDATA [11] GND_D
N. C.
N. C.
N. C.
VCC_IA
VCC_IA
VCC_IA
VCC_IA
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
VCC_IA
VCC_ IA
VCC_ IA
VCC_ IA
VCC_IA
VCC_IA
N. C.
N. C.
N. C.
PDATA [17] VCC_D
GND_D
PDATA [16] PDATA [18]
N. C.
N. C.
GND_IA
GND_IA
GND_IA
GND_IA
N. C.
N. C.
GND_A1
GND_A1
N. C.
PDATA [19]
N. C.
N. C.
VCC_IA
VCC_ IA
VCC_ IA
VCC_ IA
N. C.
N. C.
EXTRC2
EXTRC1
VCC_A1
PDATA [20] VCC_D
PDATA [21] PDATA [24]
GND_D
N. C.
N. C.
GND_IA
GND_IA
GND_IA
GND_IA
N. C.
VCC_A1
N. C.
N. C.
SDATA#
PDATA [23]
N. C.
N. C.
N. C.
GND_IA
GND_IA
N. C.
N. C.
N. C.
SDATA
N. C.
GND_A0
PDATA [22]
GND_D
PDATA [26]
N. C.
N. C.
N. C.
N. C.
N. C.
VCC_A0
GND_A0
VCC_A0
N. C.
N. C.
N. C.
PDATA [25]
PDATA [27]
N.C.
VCC_D
GND_D
FLAGI
N. C.
N. C.
VCC_A0
N. C.
N. C.
N. C.
N. C.
N. C.
PARGEN PDATA [28]
PDATA [30]
PDATA [32]
PDATA [34]
VALID
VCC_ID
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
PDATA [29]
PDATA [31]
PDATA [33]
PDATA [35]
PERR#
GND_ID
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
Note:
N.C. marked pins are not electrically connected to the dice. However, for improved thermal performance, the pins are electrically connected to each other. It is recommended to tie all N.C. pins to that supply plane with the best heat sink capability. Pin 1 Identifier Figure 13: GigaSTaR(R) INGT165B Pin Assignments (Top View)
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INGT165B / INGR165B
INGR165B RECEIVER PIN DEFINITION
Pin Name PDATA[0] PDATA[1] PDATA[2] PDATA[3] PDATA[4] PDATA[5] PDATA[6] PDATA[7] PDATA[8] PDATA[9] PDATA[10] PDATA[11] PDATA[12] PDATA[13] PDATA[14] PDATA[15] PDATA[16] PDATA[17] PDATA[18] PDATA[19] PDATA[20] PDATA[21] PDATA[22] PDATA[23] PDATA[24] PDATA[25] PDATA[26] PDATA[27] PDATA[28] PDATA[29] PDATA[30] PDATA[31] PDATA[32] PDATA[33] PDATA[34] PDATA[35] PARITY WRCLK LSYNC# RESET# FLAGO PERR# EQLSEL LOCK OSC SDATA SDATA# EXTRC1 EXTRC2 GND--D GND--ID GND--IA GND--A0 GND--A1 VCC--D VCC--ID VCC--IA VCC--A0 VCC--A1 Pin # A5 B5 A4 B4 A3 B3 A2 B2 B1 C1 D2 E3 D1 E2 E1 F2 G3 G1 H3 H2 J1 J2 L1 K3 K2 M1 L3 M2 N2 P2 N3 P3 N4 P4 N5 P5 C6 B6 N6 A6 M6 P6 C10 C7 A10 E12 E14 H13 H12 C2, C5, F3, G2, J3, L2, M5 A7, P7 G6, G7, G8, G9, J6, J7, J8, J9, K7, K8 C9, C11, D10, D14, K14, L10 G12, G13 C4, D3, F1, H1, K1, M4, N1 B7, N7 E7, E8, E9, E10, F6, F7, F8, F9, F10,F11, H6, H7, H8, H9 A11, D9, L9, L11, M9 H14, J11 Direction OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS OUTCMOS INCMOS OUTCMOS OUTCMOS INCMOS OUTCMOS INCMOS INCML INCML GND GND GND GND GND VCC VCC VCC VCC VCC Active High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High Low Low High Low High High High Description Parallel data output, Bit 0 Parallel data output, Bit 1 Parallel data output, Bit 2 Parallel data output, Bit 3 Parallel data output, Bit 4 Parallel data output, Bit 5 Parallel data output, Bit 6 Parallel data output, Bit 7 Parallel data output, Bit 8 Parallel data output, Bit 9 Parallel data output, Bit 10 Parallel data output, Bit 11 Parallel data output, Bit 12 Parallel data output, Bit 13 Parallel data output, Bit 14 Parallel data output, Bit 15 Parallel data output, Bit 16 Parallel data output, Bit 17 Parallel data output, Bit 18 Parallel data output, Bit 19 Parallel data output, Bit 20 Parallel data output, Bit 21 Parallel data output, Bit 22 Parallel data output, Bit 23 Parallel data output, Bit 24 Parallel data output, Bit 25 Parallel data output, Bit 26 Parallel data output, Bit 27 Parallel data output, Bit 28 Parallel data output, Bit 29 Parallel data output, Bit 30 Parallel data output, Bit 31 Parallel data output, Bit 32 Parallel data output, Bit 33 Parallel data output, Bit 34 Parallel data output, Bit 35 Parity output Write clock Receiver is synchronous, link is established Asynchronous reset signal FLAG output Parity error Equalizer select PLL lock indication Reference clock input, 66MHz Differential serial high-speed CML input Differential serial high-speed CML input External loop filter pin1 External loop filter pin2 Digital chip (CMOS) power supply GND Chip interface digital chip power supply GND Chip interface analog chip power supply GND Analog chip (Bipolar) power supply GND Analog chip (Bipolar) PLL circuit power supply ground Digital chip (CMOS) power supply VCC Chip interface digital chip power supply VCC Chip interface analog chip power supply VCC Analog chip (Bipolar) power supply VCC Analog chip (Bipolar) PLL circuit power supply VCC
Table 16: GigaSTaR(R) INGR165B Pin Definition
10/2003 - rev. 2.0
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INGT165B / INGR165B
INGR165B RECEIVER PIN ASSIGNMENT (TOP VIEW)
1 A B C D E F G H J K L M N P
N. C.
2
PDATA [6]
3
PDATA [4]
4
PDATA [2]
5
PDATA [0]
6
RESET#
7
GND_ID
8
N. C.
9
N. C.
10
OSC
11
VCC_A0
12
N. C.
13
N. C.
14
N. C.
PDATA [8] PDATA [9] PDATA [12]
PDATA [7] GND_D
PDATA [5] N. C.
PDATA [3] VCC_D
PDATA [1] GND_D
WRCLK
VCC_ID
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
PARITY
LOCK
N. C.
GND_A0
EQLSEL
GND_A0
N. C.
N. C.
N. C.
PDATA [10]
VCC_D
N. C.
N. C.
N. C.
N. C.
N. C.
VCC_A0
GND_A0
N. C.
N. C.
N. C.
GND_A0
PDATA [14] VCC_D
PDATA [13] PDATA [15]
PDATA [11] GND_D
N. C.
N. C.
N. C.
VCC_IA
VCC_IA
VCC_IA
VCC_IA
N. C.
SDATA
N. C.
SDATA#
N. C.
N. C.
VCC_IA
VCC_IA
VCC_IA
VCC_IA
VCC_IA
VCC_IA
N. C.
N. C.
N. C.
PDATA [17] VCC_D
GND_D
PDATA [16] PDATA [18]
N. C.
N. C.
GND_IA
GND_IA
GND_IA
GND_IA
N. C.
N. C.
GND_A1
GND_A1
N. C.
PDATA [19]
N. C.
N. C.
VCC_IA
VCC_IA
VCC_IA
VCC_IA
N. C.
N. C.
EXTRC2
EXTRC1
VCC_A1
PDATA [20] VCC_D
PDATA [21] PDATA [24] GND_D
GND_D
N. C.
N. C.
GND_IA
GND_IA
GND_IA
GND_IA
N. C.
VCC_A1
N. C.
N. C.
N. C.
PDATA [23] PDATA [26]
N. C.
N. C.
N. C.
GND_IA
GND_IA
N. C.
N. C.
N. C.
N. C.
N. C.
GND_A0
PDATA [22]
N. C.
N. C.
N. C.
N. C.
N. C.
VCC_A0
GND_A0
VCC_A0
N. C.
N. C.
N. C.
PDATA [25] VCC_D
PDATA [27] PDATA [28]
N.C.
VCC_D
GND_D
FLAGO
N. C.
N. C.
VCC_A0
N. C.
N. C.
N. C.
N. C.
N. C.
PDATA [30]
PDATA [32]
PDATA [34]
LSYNC#
VCC_ID
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
PDATA [29]
PDATA [31]
PDATA [33]
PDATA [35]
PERR#
GND_ID
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
N. C.
Note:
N.C. marked pins are not electrically connected to the dice. However, for improved thermal performance, the pins are electrically connected to each other. It is recommended to tie all N.C. pins to that supply plane with the best heat sink capability. Pin 1 Identifier Figure 14: GigaSTaR(R) INGR165B Pin Assignments (Top View)
10/2003 - rev. 2.0
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INGT165B / INGR165B
4.4 PACKAGE DIMENSIONS (12MM X 12MM PBGA)
B A Pitch
A Ball
Pitch Bottom View A1 Pin Corner A Side View
C
MILLIMETERS TYP.
0.05 0.10 0.05 0.04 0.05
A
A B C Pitch Ball
12.00 1.40 0.36 0.80 0.46
Top View Figure 15: Package Dimensions
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INGT165B / INGR165B
4.5 PACKAGE HANDLING PRECAUTIONS
BGA packages are moisture-sensitive and are delivered in sealed dry packs. The devices presented in this datasheet meet JEDEC standard 22A113B, Level 3. Handling precautions are: 1. Shelf life in sealed dry pack : 12 months at < 40 C and < 90% RH 2. After the dry pack is opened, devices that will undergo infrared reflow, vapor-phase reflow, or equivalent processing (peak package body temperature 220 C, maximum peak temperature package exposure time 10 sec) must be: a) mounted within 168 hrs at factory conditions of <=30 C / 60% RH, or b) stored at <= 20% RH or c) be baked less than 168 hrs before undergoing infrared reflow, vapor-phase reflow, or equivalent processing (peak package body temperature 220 C) 3. If baking is required, devices may be baked for : a) 192 hours at 40 C + 5 C / -0 C and < 5% RH b) 24 hours at 125 C + 5 C / -5 C (for baking above 130 C, high-temperature trays are required) 4. Precautions have to be taken against exposure of the device terminals to electrostatic discharge stress 5. The maximum ratings may not be exceeded at any time 6. At power-up and power-down sequences, all supply voltage nodes have to be ramped up and down with identical voltage ramping, otherwise the maximum rating of ID (I/O Current DC or transient per pin) can be exceeded and damage to the device may occur.
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INGT165B / INGR165B
4.6 ORDERING CODE AND PRODUCTION STATUS INFORMATION
Ordering Code INGT165B INGR165B INGSK ING_TRC ING_TRF ING_TTC ING_RRC Delivery package, minimum packing quantity (MPQ) Tray (in sealed dry pack); MPQ = 189 units Tray (in sealed dry pack); MPQ = 189 units Sample Kit (in sealed dry pack); Box containing 2 x INGT165B and 2 x INGR165B Piggyback Board w/ INGT165B and INGR165B, SUB D9 connector for cable data transmission Box; MPQ = 10 units Piggyback Board w/ INGT165B and INGR165B with fiber optic module Box; MPQ = 10 units Piggyback Board with two INGT165B, SUB D9 connector for cable data transmission Box; MPQ = 10 units Piggyback Board with two INGR165B, SUB D9 connector for cable data transmission Box; MPQ = 10 units Production Status full production full production full production full production full production full production full production
Table 17: Product Availability
Inova Semiconductors GmbH Grafinger Str. 26 D-81671 Munich, Germany Phone: +49 (0)89 / 45 74 75 - 60 Fax: +49 (0)89 / 45 74 75 - 88 Email: info@inova-semiconductors.de URL: http://www.inova-semiconductors.com
is a registered trademark of Inova Holding GmbH. is a registered trademark of Inova Semiconductors GmbH. All other trademarks or registered trademarks are the property of their respective holders. Inova Semiconductors GmbH does not assume any liability arising out of the applications or use of the product described herein; nor does it convey any license under its patents, copyright rights or any rights of others. Inova Semiconductors products are not designed, intended or authorized for use as components in systems to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. The information contained in this document is believed to be current and accurate as of the publication date. Inova Semi-conductors GmbH reserves the right to make changes at any time in order to improve reliability, function or performance to supply the best product possible. Inova Semiconductors GmbH assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. (c) Inova Semiconductors GmbH 2003. All rights reserved.
10/2003 - rev. 2.0
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